Digital Communications
VSORA meets the challenge with a development platform that allows you to select DSP-Cores with different sizes.
Our approach offers better system power control and silicon area optimization
Digital Communications (incl 5G)
The 5G NR market is driving the processing power and flexibility requirements of the digital communications system to an entirely new level. Based on individually configurable single and multicores, with user-definable number of ALUs per core the VSORA architecture has been specifically designed to fulfil these new requirements. The flexibility of the solution makes it standard agnostic, so 4G, 5G and WLAN, including Wi-Fi 6, can easily be implemented using the same hardware.
Highlights
High processing power
High processing power eliminates the need for specific coprocessors and hardware accelerators and ensures greater flexibility.
Customizable hardware
Customizable hardware with a configurable number of ALUs per core and unlimited number of cores.
Optimal algorithm mapping
Optimally maps algorithms, including non-parallel algorithms.
User defined quantization
Floating point precision can be user specified to optimize the system.
Automatic interconnect handling
Automatic handling of the interconnect between the different cores.
Low power
Lower energy consumption / power constraints.
High efficiency
- Signals handled in hardware.
- Signal memory bandwidth scales with MPU processing power.
- Multi-instructions per cycle / rich set of instructions.
Able to handle higher processing requirements
Higher processing power to handle MiMo, beamforming and carrier aggregation requirements.
Futureproof
Futureproof should standards evolve.
Algorithms mapped to different cores
Easy mapping of algorithms to different cores.
Easy system programming
Compilation platform separates codes running in the different cores.
Platform independent design flow
High-level, platform independent design flow (C++/Matlab-like).
Optimized silicon area
Silicon area optimized to required processing power.
Multi-core MPU Architecture
- Unlimited number of cores
- User-selectable number of ALUs in each core
- User-defined accuracy
- User-defined memory size