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Development Environment

Development Flow Overview


An innovative software-oriented development flow eliminates design risks and accomodates evolving standards without silicon re-spins. The pioneering flow accelerates the development of a new system and reduces the time to market. System code is implementation agnostic and multi-core configurations can be changed, moving to more advanced technology nodes. Each core can scale in processing power and computation accuracy. The compiler separates code running on the host and on the VSORA processor (single or multi-core).


High-level Code Design

System design (high level code) is platform independent.

Easy Mapping To Several Cores

Easy mapping of the algorithms to the different cores.

Automatic Interconnect Handling

Automatic handling of the interconnect between different cores.

Code Separation Handled By Compiler

Compilation platform separates codes running in the different cores.

Same Code For All Simulations

Simulation platforms with Matlab-like/TensorFlow-like code down to RTL with the same high-level code.

Easily Facilitates "What-If" Scenarios

Simulation tools provide quick utilization, performance, area and power estimates, and easily facilitates “What-If” scenarios.

Cloud Simulation Possibility

Architecture mapped on Amazon Web Services Cloud FPGA makes cloud simulation on FPGA possible.

Design Flow

Software-Driven vs. Traditional

VSORA Software-Driven Design Flow

Software-Driven Design Flow


  • Lower design risk
  • Reduced cost
  • Faster development cycle
  • Shorter Time-To-Market
  • Standard evolutions without silicon re-spin
Traditional Design Flow

Traditional Design Flow


  • Four different, large engineering teams
  • Very slow process
  • Exceedingly expensive

Development Flow

Compiler separes code running on MPU and host

Complex System Implementations Simplified

The system code is implemented in high-level language, using, for example, C++ or Matlab-like / Tensorflow-like code.

The code is written as if everything is executed on the host, and at compilation the smart compiler will separate code running on the VSORA MPU from the code running on the host. For the designer it will look as if everything is executed on the host processor.

Using one code for both algorithms and the embedded software makes the design process faster and simpler, which results in a minimal learning curve.