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Artificial Intelligence

VSORA offers the most flexible solution on the market, by giving the user the ability to select the best combination of performance, power and cost.
Outstanding performance from IoT to ADAS and beyond!

Artificial Intelligence

Artificial Intelligence

The only constant in the world of AI is change. Higher processing requirements and new algorithms are introduced regularly. In this environment a solution must have high flexibility and programmability, since everything evolves rapidly, making any hard-coded approach non-viable from the start. The processing power requirements keep increasing as new AI inference and real-time processing requisites are announced. Edge AI needs low latency as well as lower energy consumption and has power constraints. Ultimately it comes down to cost = silicon area.

Highlights

Fully programmable solution

No pre-defined hardware blocks limiting efficiency. Can be re-programmed on the fly, and allows new code to be run without silicon re-spin.

High-level support

High-level framework support (TensorFlow, Caffe2, PyTorch, ONNX). Never any need to revert to low-level programming.

Scalable core

Scalable number of MACs in a singe core. User selectable between 256 and 65,536 MACs/core.

Very high memory bandwidth

Very high memory bandwidth enable loading of high number of MACs without performance impact.

No need for hardware accelerators

The flexible and highly efficient VSORA MPU cores eliminates the need for any external hardware accelerators.

Highly scalable

Solution works from IoT to ADAS and beyond.

Algorithm agnostic

Solution is algorithm agnostic - CNN, RNN, other ...  If an algorithm can be expressed in Matlab, Tensorflow (or similar), C++ etc. it will run on the core(s).

Graph support

In addition to high-level language support, a user can also utilize the VSORA graph compiler to simplify programming.

Unlimited number of parallel cores

There is no limit on the number of cores that can work in parallel. From one to many!

No memory bandwidth bottleneck

No memory bandwidth bottleneck as data memory bandwidth follows processing power.

Compute precision independent of performance

Compute precision only impacts silicon area, but performance is identical regardsless of precision.

TOPs is not enough!

Efficiency and latency are other key factors to consider when planning the solution.

Below are 3 examples running ResNet50v1

All configurations using 65,536 MACs and providing 288 TOPs.

 

Click on the images below to find out more.

Each core: 72 TOPs
Latency: 0.25 ms.
15,700 img/sec

Each core: 18 TOPs
Latency: 0.62 ms.
25,800 img/sec

Each core: 4.5 TOPs
Latency: 2.02 ms.
31,500 img/sec