This review was written by Lauro Rizzatti and posted on www.eeweb.com (Aspencore Network) :
Tuesday, November 6th, 2018
VSORA, a startup from Paris, recently emerged from stealth mode with a new approach to accelerate 5G broadband design. Khaled Maalej, its founder and CEO, and I recently talked about VSORA’s multicore digital signal processing (DSP) intellectual property (IP) and development flow for 5G and AI applications.
Serial entrepreneur Maalej and VSORA’s founders come from DiBcom, a Parisian startup (now part of Parrot) that designed chipsets for low-power mobile TV and radio reception. Over several years at DiBcom, they noticed that the development of high-bandwidth baseband systems was not evolving and improving. They determined that this was due to the inadequacy of the heavily sequential development flow that forced a time-consuming feedback loop between algorithmic designers and DSP hardware developers.
As Maalej continued, he explained that algorithmic engineers would devise an algorithm in the MATLAB environment. Once they trusted that their creation provided satisfactory results, they would freeze the algorithm and pass it over to the DSP developers for implementation. That group would spend a couple of months implementing a thoroughly verified register transfer level (RTL) design of the algorithm.
- The AspenCore Network : "A more efficient flow to support DSP development groups, such as VSORA's, could help to ensure the success of 5G"
“At this stage, the rubber met the road,” remarked Maalej. The overall performance — speed, area, and power — of the DSP design would be measured against target specifications before DSP developers would release it to the broadband system engineers and embedded software developers for deployment in the broadband system design. If, as is often the case, the overall performance did not meet specifications, design iterations took place between the algorithmic engineers who readjusted the algorithms and DSP hardware developers who had to implement the modifications.
The result was a delay in the release of the broadband design by several months compounded by an increase of the risk that the design would be less than optimal.
“DSPs have been around for several decades and these challenges haven’t been addressed in the design center,” noted Maalej. The current DSP technology does not offer enough processing power to address the demands of today’s high-bandwidth broadband systems, such as 5G wireless applications.
Designers add DSP co-processors around the programmable DSP that implements the brains of the system. DSP co-processors are hardwired algorithms. If the designer did not provide enough power for the application or if the power consumption exceeded the allocated quota, it had to be modified to meet requirements. Iterations to increase processing power or decrease power consumption cause costly delays on the schedule.
The VSORA founders identified their next challenger by changing the scenario through DSP hardware based on a multicore approach called the multicore signal processor (MSP). VSORA (for Vectorized Software Radio) offers high processing power as well as low power consumption without compromising the flexibility inherent to its programmability.
“High power is necessary to cope with complex algorithms such as those required by 5G broadband designs,” affirmed Maalej. MSP incorporates a signal manager to handle up to tri-dimensional signal matrices in hardware using high-bandwidth memory to ensure that embedded arithmetic logic units (ALUs) are fully utilized. Also, a large set of instructions executable in a single clock cycle plus support for multiple instructions per cycle increase the processing power of MSP.
The development flow eliminates the need to generate low-level implementation code by keeping the source code in a MATLAB-like format created by algorithmic engineers as the reference. The VSORA MSP development flow automatically compiles the source code to binary format that will run on the MSP. Scientists can evaluate the speed, area, and power of their algorithms easily and in a very short time.
The VSORA DSP development flow is similar to one used by software engineers. (Source: VSORA)
As a result, algorithmic engineers are in charge and control the development flow with full visibility of the end product. The system cost optimization is dependent on the selected algorithms and can be estimated at the beginning of the project. Algorithm engineers can analyze the cost of their algorithms and readjust or change them as necessary, thereby easing the development and maintenance of complex systems.
The new MSP flow permits mixing signal processing code and system embedded software code in the same files for broadband system engineers and algorithmic engineers to interact with each other’s files, shortening the development cycle.
Yes, it is similar to a software development flow, said Maalej. “By removing the DSP hardware implementation from the development flow and giving algorithmic engineers full control of the process, the flow is rather similar to a software flow, making it faster, more efficient, and less expensive.”
“Complex systems cannot be mapped to a single core” he added. The MSP allows algorithmic engineers to select the number of cores estimated for the task and size each for processing power — that is, decide how many ALUs per core — as well as for computation accuracy.
Asked about the difficulty in mapping a complex system for 5G and AI applications to MSP, Maalej said: “In general, algorithmic engineers are not familiar with implementation technologies. This is why we simplified the development flow to allow them to carry out the implementation in an easy way. They do not have to change their system simulation to try different hardware configurations or change the number of cores — from three to four cores, for example. They just need to specify the hardware in a separated file with one of two lines of simple code.”
The emerging 5G wireless network holds the promise of high data rate, reduced latency, energy savings, cost reduction, higher system capacity, and massive device connectivity. A more efficient flow to support DSP development groups, such as VSORA’s, could help to ensure the success of 5G.