Next generation AI
Next Generation AI

ResNet-50 - 25,854 images /second & 290 TOPs with 64k MACs

Highly efficient, field upgradeable solutions for IoT through to ADAS and beyond

True 5G
Low Power Multicore DSP

Full 5G performance using flexible design with high processing power

Algorithms

New Era

in digital communications algorithms

No hardware limitations to the algorithm implementation
Development Flow

Disruptive Development Flow

Full and quick visibility on algorithm's DSP load for better system optimisation
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Solutions

Two challenges pave the path to the future of AI and digital communications: escalating processing power to accelerate computation of fast-growing algorithms, and widening memory bandwidth to handle unprecedented amounts of data with minimal latency. Today’s systems are inflexible and cannot meet the challenges. What's needed is a system that can handle today’s memory bandwidth and tomorrow’s new algorithms without changing hardware. VSORA provides a future-proof, highly efficient solution that eliminates the need for dedicated hardware accelerators. VSORA gives you the flexibility of an FPGA with the performance of an ASIC.

AI

VSORA has developed a unique, algorithm-agnostic architecture that allows you to optimize power, performance and silicon size. With a single core scalable from 256 to 65,536 MACs and the ability to design a system with multiple cores, the solution gives the user a wide range of choices. An innovative combination of software and hardware can reconfigure a system in a single clock cycle, to accelerate all current and future algorithms without hardware changes.

AI v3

5G, Wi-Fi 6 And Other Digital Communications

The implementation of MiMo and Beamforming for 5G, Wi-Fi 6 or other standards is a daunting task that, in addition to signal synchronization, requires the use of DSP cores with ample processing power. VSORA provides a solution with a flexible, user-defined choice of processing power. Ranging from single core to multiple cores, the VSORA groundbreaking and efficient approach achieves better system power control and optimized silicon area.

Digital Communications